华东区培训课程及时间安排
地点: 上海培训中心
| 时间 | 课程 | 内容大纲 |
| Mar.17,2015 | PrimeTime Training | 1.Introduction&Overview |
| 2.Does Your Design Meet Timing | ||
| 3.Objects,Attributes,Collections | ||
| 4.Constraints in a Timing Report | ||
| 5.Timing Arcs in a Timing Report | ||
| 6.Control Which Paths are Reported | ||
| 7.Summary Report+Wrap Up | ||
| 8.Create a Setup File and Run Script | ||
| 9.Getting to Know Your Clocks | ||
| 10.Anasysis Type and Back Annotation | ||
| Apr.23,2015 | Synplify Premier Training | 1.Introduction |
| 2.Getting Started | ||
| 3.Timing Optimizations | ||
| 4.Design Analysis and Debugging | ||
| 5.Handling IPs | ||
| 6.FPGA Vendor Specific Topics | ||
| Jun.4.2015 | Verdi3 Training | 1 Debug in Source Code View |
| 2 Debug in Waveform View | ||
| 3 Debug in Schematic View | ||
| 4 Debug in FSM view | ||
| 5 Debug in Temporal Flow View | ||
| Jul.28,2014 | HAPS Training | 1.HAPS Overview |
| 2.HDL Bridge Co-Simulation Overview | ||
| 3.Overall HDL Bridge Design Flow | ||
| 4.Supported Platforms | ||
| 5.Limitations of HDL Bridge | ||
| 6.HDL Bridge Co-Simulation-Demo | ||
| Sep.9 | VCSMX Training | 1.VCS Simulation Basics |
| 2.VCS Debugging Basics | ||
| 3.Debugging with DVE | ||
| 4.Post-Processing with VCD+ Files | ||
| 5.Debugging Simulation Mismatches | ||
| 6.Fast RTL level Verification | ||
| 7.Fast Gate Level Verification | ||
| 8.Code Coverage | ||
| Oct.22,2015 | Synplify Premier Training | 1.Introduction |
| 2.Getting Started | ||
| 3.Timing Optimizations | ||
| 4.Design Analysis and Debugging | ||
| 5.Handling IPs | ||
| 6.FPGA Vendor Specific Topics | ||
| Dec.8,2015 | PrimeTime Training | 1.Introduction&Overview |
| 2.Does Your Design Meet Timing | ||
| 3.Objects,Attributes,Collections | ||
| 4.Constraints in a Timing Report | ||
| 5.Timing Arcs in a Timing Report | ||
| 6.Control Which Paths are Reported | ||
| 7.Summary Report+Wrap Up | ||
| 8.Create a Setup File and Run Script | ||
| 9.Getting to Know Your Clocks | ||
| 10.Anasysis Type and Back Annotation |
北方区培训课程及时间安排表
地点: 北京培训中心
|
时间 |
课程 |
内容大纲 |
|
2015/01/23 |
SiT_HAPS_Co-Sim_Training |
1 HAPS 6x Overview |
| 2 HDL Bridge Co-Simulation Overview | ||
| 3 Overall HDL Bridge Design Flow | ||
| 4 HDL Bridge Co-Simulation – Demo | ||
| 5 Demo – Step-by-Step Implementation | ||
|
2015/03/27 |
SiT_Verdi3_Training |
1 Debug in Source Code View |
| 2 Debug in Waveform View | ||
| 3 Debug in Schematic View | ||
| 4 Debug in FSM view | ||
| 5 Debug in Temporal Flow View | ||
|
2015/05/22 |
SIT_PrimeTime_Training |
1 Introduction to PrimeTime |
| 2 Working with PrimeTime | ||
| 3 Constraints in a Timing Analysis | ||
| 4 Timing Exceptions | ||
| 5 Generating Reports | ||
| 6 Graphical User Interface | ||
|
2015/07/24 |
SiT_Synplify_Premier_Training |
1 FPGA Synthesis Design Flows |
| 2 Analyzing the Results | ||
| 3 Inferring Hign-Level Objects | ||
| 4 Specifying Design-Level Optimizations | ||
| 5 Fast Synthesis | ||
| 6 Working with IP Input | ||
| 7 Clock Conversion | ||
| 8 Analyzing Power Activity | ||
| 9 Verifying Results with Formality | ||
|
2015/10/23 |
SiT_VCSMX_Training |
1 What is VCSMX |
| 2 VCS MX Simulation Basics | ||
| 3 Gate Netlist Simulation Flow | ||
| 4 Debugging With DVE | ||
| 5 Introducing Coverage Technology | ||
| 6 Generating Coverage Database | ||
| 7 Viewing Coverage Reports Using the DVE | ||
|
2015/11/27 |
SIT_Formality_Training |
1 Introduction to Equivalence Checking |
| 2 Using Formality | ||
| 3 Documentation and Help | ||
| 4 Simple logic cones and failing points | ||
|
2015/12/18 |
Synopsys FPGA design and Verification Solution |
1 Synopsys FPGA Solution Overview |
| 2 Synopsys FPGA-Based Prototyping |
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